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ISL9000A
Data Sheet January 10, 2007 FN6391.0
Dual LDO with Low Noise, Very High PSRR, and Low IQ
ISL9000A is a high performance dual LDO capable of sourcing 300mA current from each output. It has a low standby current and very high PSRR and is stable with output capacitance of 1F to 10F with ESR of up to 200m. The device integrates an individual Power-On-Reset (POR) function for each output. The POR delay for VO2 can be externally programmed by connecting a timing capacitor to the CPOR pin. The POR delay for VO1 is internally fixed at approximately 2ms. A reference bypass pin is also provided for connecting a noise filtering capacitor for low noise and high-PSRR applications. The quiescent current is typically only 42A with both LDO's enabled and active. Separate enable pins control each individual LDO output. When both enable pins are low, the device is in shutdown, typically drawing less than 0.1A. Several combinations of voltage outputs are standard. Others are available on request. Output voltage options for each LDO range from 1.2V to 3.6V.
Features
* Integrates two 300mA high performance LDO's * Excellent Transient Response To large current steps * 1.8% accuracy over all operating conditions * Excellent load regulation: < 0.1% voltage change across full range of load current * Low output noise: typically 30Vrms @ 100A (1.5V) * Very high PSRR: 90dB @ 1kHz * Extremely low quiescent current: 42A (both LDOs active) * Wide input voltage capability: 2.3V to 6.5V * Low dropout voltage: typically 200mV @ 300mA * Stable with 1F-10F ceramic capacitors * Separate enable and POR pins for each LDO * Soft-start and staged turn-on to limit input current surge during enable * Current limit and overheat protection * Tiny 10 Ld 3x3mm DFN package
Pinout
ISL9000A (10 LD 3X3 DFN) TOP VIEW
* -40C to +85C operating temperature range * Pb-free plus anneal available (RoHS compliant)
Applications
10 VO1 9 8 7 6 VO2 POR2 POR1 GND
VIN 1 EN1 2 EN2 3 CBYP 4 CPOR 5
* PDAs, Cell Phones and Smart Phones * Portable Instruments, MP3 Players * Handheld Devices including Medical Handheld
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL9000A Ordering Information
PART NUMBER (Notes 1, 2, 3) ISL9000AIRNNZ ISL9000AIRNJZ ISL9000AIRNFZ ISL9000AIRNCZ ISL9000AIRMNZ ISL9000AIRMMZ ISL9000AIRMGZ ISL9000AIRLLZ ISL9000AIRKNZ ISL9000AIRKKZ ISL9000AIRKJZ ISL9000AIRKFZ ISL9000AIRKPZ ISL9000AIRKCZ ISL9000AIRJNZ ISL9000AIRJMZ ISL9000AIRJRZ ISL9000AIRJCZ ISL9000AIRJBZ ISL9000AIRGPZ ISL9000AIRGCZ ISL9000AIRFJZ ISL9000AIRFDZ ISL9000AIRFCZ ISL9000AIRPLZ ISL9000AIRPPZ ISL9000AIRCJZ ISL9000AIRCCZ ISL9000AIRBLZ ISL9000AIRBJZ ISL9000AIRBCZ ISL9000AIRBBZ NOTES: 1. Add -T to part number for tape and reel. 2. For other output voltages, contact Intersil Marketing. 3. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING DEYA DEWA DEVA DETA DESA DERA DEPA DENA DELA DEKA DEJA DEHA DEMA DEGA DEEA DEDA DEFA DECA DEBA DDYA DDWA DDVA DDTA DDSA DFBA DFCA DDRA DDPA DDNA DDMA DDLA DDKA VO1 VOLTAGE (V) 3.3 3.3 3.3 3.3 3.0 3.0 3.0 2.9 2.85 2.85 2.85 2.85 2.85 2.85 2.8 2.8 2.8 2.8 2.8 2.7 2.7 2.5 2.5 2.5 1.85 1.85 1.8 1.8 1.5 1.5 1.5 1.5 VO2 VOLTAGE (V) TEMP RANGE (C) 3.3 2.8 2.5 1.8 3.3 3.0 2.7 2.9 3.3 2.85 2.8 2.5 1.85 1.8 3.3 3.0 2.6 1.8 1.5 1.85 1.8 2.8 2.0 1.8 2.9 1.85 2.8 1.8 2.9 2.8 1.8 1.5 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN PKG DWG. # L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C
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FN6391.0 January 10, 2007
ISL9000A
Absolute Maximum Ratings
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN+0.3)V
Thermal Information
Thermal Resistance (Notes 1, 2) JA (C/W) JC (C/W) 3x3 DFN Package . . . . . . . . . . . . . . . . 50 10 Junction Temperature Range . . . . . . . . . . . . . . . . .-40C to +125C Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300C
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40C to +85C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 to 6.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. JC, "case temperature" location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40C to +85C; VIN = (VO+0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1F; CO = 1F; CBYP = 0.01F; CPOR = 0.01F SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER DC CHARACTERISTICS Supply Voltage Ground Current
VIN Quiescent condition: IO1 = 0A; IO2 = 0A IDD1 IDD2 One LDO active Both LDO active @+25C
2.3
6.5
V
25 42 0.1 1.9 1.6 2.1 1.8
32 52 1.0 2.3 2.0 +0.7 +0.8 +1.8
A A A V V % % % mA
Shutdown Current UVLO Threshold
IDDS VUV+ VUV-
Regulation Voltage Accuracy
Initial accuracy at VIN = VO+0.5V, IO = 10mA, TJ = +25C VIN = VO+0.5V to 5.5V, IO = 10A to 300mA, TJ = +25C VIN = VO+0.5V to 5.5V, IO = 10A to 300mA, TJ = -40C to +125C
-0.7 -0.8 -1.8 300 350 475 300 250 200 145 110
Maximum Output Current Internal Current Limit Dropout Voltage (Note 4)
IMAX ILIM VDO1 VDO2 VDO3
Continuous
600 500 400 325
mA mV mV mV C C
IO = 300mA; VO < 2.5V IO = 300mA; 2.5V VO 2.8V IO = 300mA; VO > 2.8V
Thermal Shutdown Temperature
TSD+ TSD-
AC CHARACTERISTICS Ripple Rejection (Note 3) IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1F @ 1kHz @ 10kHz @ 100kHz Output Noise Voltage (Note 3) DEVICE START-UP CHARACTERISTICS Device Enable TIme TEN Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO(nom) 250 500 s IO = 100A, VO = 1.5V, TA = 25C, CBYP = 0.1F BW = 10Hz to 100kHz 90 70 50 30 dB dB dB Vrms
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FN6391.0 January 10, 2007
ISL9000A
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40C to +85C; VIN = (VO+0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1F; CO = 1F; CBYP = 0.01F; CPOR = 0.01F (Continued) SYMBOL TSSR TEST CONDITIONS Slope of linear portion of LDO output voltage ramp during start-up MIN TYP 30 MAX 60 UNITS s/V
PARAMETER LDO Soft-Start Ramp Rate EN1, EN2 PIN CHARACTERISTICS Input Low Voltage Input High Voltage Input Leakage Current Pin Capacitance
VIL VIH IIL, IIH CPIN Informative
-0.3 1.4
0.5 VIN+0.3 0.1 5
V V A pF
POR1, POR2 PIN CHARACTERISTICS POR1, POR2 Thresholds VPOR+ VPORPOR1 Delay TP1LH TP1HL POR2 Delay TP2LH TP2HL POR1, POR2 Pin Output Low Voltage POR1, POR2 Pin Internal Pull-Up Resistance NOTES: 3. Guaranteed by design and characterization. 4. VOx = 0.98 * VOx(NOM); Valid for VOx greater than 1.85V. VOL RPOR @IOL = 1.0mA 78 100 CPOR = 0.01F 100 As a percentage of nominal output voltage 91 87 1.0 94 90 2.0 25 200 25 0.2 180 300 97 93 3.0 % % ms s ms s V k
EN1 EN2
TEN VPOR+ VPOR+ VO1 VO2
VPOR-
VPOR-
tP1LH tP2LH
tP1HL tP2HL
POR1 POR2
FIGURE 1. TIMING PARAMETER DEFINITION
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FN6391.0 January 10, 2007
ISL9000A Typical Performance Curves
0.8 0.6 OUTPUT VOLTAGE, VO (%) 0.4 0.2 -40C 0.0 +25C -0.2 -0.4 -0.6 -0.8 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2 6.6 INPUT VOLTAGE (V) +85C VO = 3.3V ILOAD = 0mA OUTPUT VOLTAGE CHANGE (%) 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 +85C -0.04 -0.06 -0.08 -0.10 0 50 100 150 200 250 300 350 400 +25C -40C VIN = 3.8V VO = 3.3V
LOAD CURRENT - IO (mA)
FIGURE 2. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT)
0.10 0.08 OUTPUT VOLTAGE CHANGE (%) 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 -40 VIN = 3.8V VO = 3.3V ILOAD = 0mA
FIGURE 3. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
3.4 VO = 3.3V 3.3 OUTPUT VOLTAGE, VO (V) IO = 0mA
3.2 IO = 150mA 3.1 IO = 300mA 3.0
2.9
2.8 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 3.1 3.6 4.1 4.6 5.1 5.6 6.1 6.5 INPUT VOLTAGE (V)
FIGURE 4. OUTPUT VOLTAGE CHANGE vs TEMPERATURE
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT)
350
2.9 IO = 0mA 2.8 OUTPUT VOLTAGE, VO (V) VO = 2.8V DROPOUT VOLTAGE, VDO (mV)
300 250 VO = 2.8V 200 VO = 3.3V 150 100 50 0
2.7 IO = 150mA 2.6 IO = 300mA 2.5
2.4
2.3 2.6
3.1
3.6
4.1
4.6
5.1
5.6
6.1
6.5
0
50
100
INPUT VOLTAGE (V)
150 200 250 OUTPUT LOAD (mA)
300
350
400
FIGURE 6. OUTPUT VOLTAGE vs INPUT VOLTAGE (2.8V OUTPUT)
FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT
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FN6391.0 January 10, 2007
ISL9000A Typical Performance Curves
350 VO = 3.3V 300 DROPOUT VOLTAGE, VDO (mV) GROUND CURRENT (A) 250 +85C 200 150 100 50 0 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 400 +25C -40C 50 +125C 45 +25C -40C
(Continued)
55
40
35 VO1 = 3.3V VO2 = 2.8V IO(BOTH CHANNELS) = 0A 25 3.0 3.5 4.0 4.58 5.0 5.5 6.0 6.5
30
INPUT VOLTAGE (V)
FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE
200 180
55
50 160 GROUND CURRENT (A) 140 120 100 80 60 40 20 0 0 50 100 150 200 250 300 350 400 LOAD CURRENT (mA) VIN = 3.8V VO1 = 3.3V VO2 = 2.8V -40C +85C +25C GROUND CURRENT (A) 45
40
35 VIN = 3.8V VO = 3.3V ILOAD = 0A BOTH OUTPUTS ON 25 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125
30
FIGURE 10. GROUND CURRENT vs LOAD
FIGURE 11. GROUND CURRENT vs TEMPERATURE
3.5 5 VIN 4 VOLTAGE (V) 3 2 1 0 VO2 VO1 VO1 = 3.3V VO2 = 2.8V IL1 = 300mA IL2 = 300mA VOLTAGE (V) 3.0 2.5 POR2 2.0 1.5 1.0 VO2 0.5 0 VO1 POR1 VO1 = 3.3V VO2 = 2.8V IL1 = 300mA IL2 = 300mA CPOR = 0.1F
0
1
2
3
4 5 TIME (s)
6
7
8
9
10
0
0.5
1.0
1.5
2.0
2.5 3.0 TIME (s)
3.5
4.0
4.5
5.0
FIGURE 12. POWER-UP/POWER-DOWN
FIGURE 13. POWER-UP/POWER-DOWN WITH POR SIGNALS
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FN6391.0 January 10, 2007
ISL9000A Typical Performance Curves
VO2 (10mV/DIV) VIN = 5.0V VO1 = 3.3V VO2 = 2.8V IL1 = 300mA IL2 = 300mA CL1, CL2 = 1F CBYP = 0.01F
(Continued)
VO = 3.3V ILOAD = 300mA CLOAD = 1F CBYP = 0.01F 4.3V 3.6V
3 2 1 0 5 0
VO1 (V)
VEN (V)
10mV/DIV
0
100
200
300
400
500
600
700
800
900 1000 400s/DIV
TIME (s)
FIGURE 14. TURN ON/TURN OFF RESPONSE
FIGURE 15. LINE TRANSIENT RESPONSE (3.3V OUTPUT)
VO = 2.8V ILOAD = 300mA CLOAD = 1F CBYP = 0.01F 4.2V 3.5V VO = 1.8V VIN = 2.8V VO (25mV/DIV)
10mV/DIV
300mA ILOAD 100A
400s/DIV
100s/DIV
FIGURE 16. LINE TRANSIENT RESPONSE (2.8V OUTPUT)
FIGURE 17. LOAD TRANSIENT RESPONSE
100 90 80 70 PSRR (dB) 60 50 40 30 20 10 0 0.1k 1k 10k 100k FREQUENCY (kHz) 1M VIN = 3.6V VO = 1.8V IO = 10mA CBYP = 0.1F CLOAD = 1F
1000 SPECTRAL NOISE DENSITY (nV/Hz)
100
10 VIN = 3.6V VO = 1.8V ILOAD = 10mA 1 CBYP = 0.1F CIN = 1F CLOAD = 1F 0.1 10
100
1k 10k FREQUENCY (Hz)
100k
1M
FIGURE 18. PSRR vs FREQUENCY
FIGURE 19. SPECTRAL NOISE DENSITY vs FREQUENCY
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FN6391.0 January 10, 2007
ISL9000A Pin Description
PIN # 1 2 3 4 PIN NAME VIN EN1 EN2 CBYP TYPE Analog I/O Low Voltage Compatible CMOS Input Low Voltage Compatible CMOS Input Analog I/O Supply Voltage/LDO Input: Connect a 1F capacitor to GND. LDO-1 Enable. LDO-2 Enable. Reference Bypass Capacitor Pin: Optionally connect capacitor of value 0.01F to 1F between this pin and GND to tune in the desired noise and PSRR performance. POR2 Delay Setting Capacitor Pin: Connect a capacitor between this pin and GND to delay the POR2 output release after LDO-2 output reaches 94% of its specified voltage level. (200ms delay per 0.01F). GND is the connection to system ground. Connect to PCB Ground plane. Open-drain POR Output for LDO-1 (active-low): Internally connected to VO1 through 100k resistor. Open-drain POR Output for LDO-2 (active-low): Internally connected to VO2 through 100k resistor. LDO-2 Output: Connect capacitor of value 1F to 10F to GND (1F recommended). LDO-1 Output: Connect capacitor of value 1F to 10F to GND (1F recommended). DESCRIPTION
5
CPOR
Analog I/O
6 7 8 9 10
GND POR1 POR2 VO2 VO1
Ground Open Drain Output (1mA) Open Drain Output (1mA) Analog I/O Analog I/O
Typical Application
ISL9000A VIN (2.3-6.5V) ON ENABLE 1 OFF ON ENABLE 2 OFF 1 2 3 4 5 C1 C2 C3 10 VIN EN1 EN2 CBYP CPOR VO1 9 VO2 8 POR2 7 POR1 6 GND C4 C5 VOUT1 TOO LOW VOUT2 TOO LOW VOUT1 OK VOUT2 OK VOUT2 RESET 2 (200ms DELAY, C3 = 0.01F) RESET 1 (2ms DELAY) VOUT1
C1, C4, C5: 1F X5R CERAMIC CAPACITOR C2: 0.1F X7R CERAMIC CAPACITOR C3: 0.01F X7R CERAMIC CAPACITOR
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FN6391.0 January 10, 2007
ISL9000A Block Diagram
VIN
VO1 VO2 LDO ERROR AMPLIFIER
VO1
~1.0V VREF TRIM POR COMPARATOR 1V VOK1 POR1 LDO-2 QEN1 QEN2 VOK2 POR2 VO2
IS1 LDO-1
QEN1
IS1
IS2
VO1 100k
EN1 EN2 CBYP UVLO
CONTROL LOGIC
POR2 VOK2 POR2 DELAY
100k
BANDGAP AND TEMPERATURE SENSOR
VO2
VOLTAGE REFERENCE GENERATOR
1.00V 0.94V 0.90V
VOK1
POR1 DELAY
POR1
CPOR
GND
Functional Description
The ISL9000A contains two high performance LDO's. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9000A adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, staged turn-on and soft-start. Smart thermal shutdown protects the device against overheating. Staged turn-on and soft-start minimize start-up input current surges without causing excessive device turn-on time.
mode. During this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1A. When one or both of the enable pins are asserted, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least about 2.1V. Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry power-up. Once the references are stable, a fast-start circuit quickly charges the external reference bypass capacitor (connected to the CBYP pin) to the proper operating voltage. After the bypass capacitor has been charged, the LDO's power-up in their specified sequence. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30s/V to minimize current surge.
Power Control
The ISL9000A has two separate enable pins, EN1 and EN2, to individually control power to each of the LDO outputs. When both EN1 and EN2 are low, the device is in shutdown
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FN6391.0 January 10, 2007
ISL9000A
If EN1 is brought high, and EN2 goes high before the VO1 output stabilizes, the ISL9000A delays the VO2 turn-on until the VO1 output reaches its target level. If EN2 is brought high, and EN1 goes high before VO2 starts its output ramp, then VO1 turns on first and, the ISL9000A delays the VO2 turn-on until the VO1 output reaches its target level. If EN2 is brought high, and EN1 goes high after VO2 starts its output ramp, then the ISL9000A immediately starts to ramp up the VO1 output. If both EN1 and EN2 are brought high at the same time, the VO1 output has priority, and is always powered up first. During operation, whenever the VIN voltage drops below about 1.8V, the ISL9000A immediately disables both LDO outputs. When VIN rises back above 2.1V, the device re-initiates its start-up sequence and LDO operation will resume automatically. The resistor division ratio is programmed in the factory to one of the following output voltages: 1.5V, 1.8V, 1.85, 2.5V, 2.6V, 2.7V, 2.8V, 2.85V, 2.9, 3.0, and 3.3V.
Power-On Reset Generation
Each LDO has a separate Power-on Reset signal generation circuit which outputs to the respective POR pins. The POR signal is generated as follows: A POR comparator continuously monitors the output of each LDO. The LDO enters a power-good state when the output voltage is above 94% of the expected output voltage for a period exceeding the LDO PGOOD entry delay time (see below). In the power-good state, the open-drain PORx output is in a high-impedance state. An internal 100k pull-up resistor pulls the pin up to the respective LDO output voltage. An external resistor can be added between the PORx output and the LDO output for a faster rise time, however, the PORx output should not connect through an external resistor to a supply greater than the associated LDO voltage. The power-good state is exited when the LDO output falls below 90% of the expected output voltage for a period longer than the PGOOD exit delay time. While power-good is false, the ISL9000A pulls the respective POR pin low. For LDO-1, the PGOOD entry delay time is fixed at about 2ms while the PGOOD exit delay is about 25s. For LDO-2, the PGOOD entry and exit delays are determined by the value of the external capacitor connected to the CPOR pin. For a 0.01F capacitor, the entry and exit delays are 200ms and 25s respectively. Larger or smaller capacitor values will yield proportionately longer or shorter delay times. The POR exit delay should never be allowed to be less than 10s to ensure sufficient immunity against transient induced false POR triggering.
Reference Generation
The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. The filter includes the external capacitor connected to the CBYP pin. A 0.01F capacitor connected CBYP implements a 100Hz lowpass filter, and is recommended for most high performance applications. For the lowest noise application, a 0.1F or greater CBYP capacitor should be used. This filters the reference noise below the 10Hz to 1kHz frequency band, which is crucial in many noise-sensitive applications. The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference, POR detection thresholds, and other voltage references required for current generation and over-temperature detection. The current generator provides the references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination.
Overheat Detection
The bandgap provides a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about 145C, one or both of the LDO's momentarily shut down until the die cools sufficiently. In the overheat condition, only the LDO sourcing more than 50mA will be shut off. This does not affect the operation of the other LDO. If both LDOs source more than 50mA and an overheat condition occurs, both LDO outputs are disabled. Once the die temperature falls back below about 110C, the disabled LDO(s) are re-enabled and soft-start automatically takes place. The ISL9000A provides short-circuit protection by limiting the output current to about 475mA. If short circuited, an output current of 475mA will cause die heating. If the short circuit lasts long enough, the overheat detection circuit will turn off the output.
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9000A provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1F to 10F output capacitor that has a tolerance better than 20% and ESR less than 200m. The design is performance-optimized for a 1F capacitor. Unless limited by the application, use of an output capacitor value above 4.7F is not normally needed as LDO performance improvement is minimal. Each LDO uses an independently trimmed 1V reference. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. 10
FN6391.0 January 10, 2007
ISL9000A Dual Flat No-Lead Plastic Package (DFN)
2X 0.10 C A A D 2X 0.10 C B
L10.3x3C
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A
E
MIN 0.85 -
NOMINAL 0.90 0.20 REF
MAX 0.95 0.05
NOTES -
A1 A3 b D
6 INDEX AREA TOP VIEW B
0.20
0.25 3.00 BSC
0.30
5, 8 -
D2
// 0.10 C 0.08 C
2.33
2.38 3.00 BSC
2.43
7, 8 -
E E2 e k L 0.20 0.35 1.59
A C SEATING PLANE SIDE VIEW A3
1.64 0.50 BSC 0.40 10 5
1.69
7, 8 -
0.45
8 2 3 Rev. 1 4/06
D2 (DATUM B) 1 2 D2/2
7
8
N Nd NOTES:
NX k E2
6 INDEX AREA (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
E2/2 NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) 9L 5 0.10 M C A B
6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2.
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN6391.0 January 10, 2007

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